For example, to form a pattern on semiconductor wafer, coating agent called resist is applied on the semiconductor wafer and the semiconductor wafer is irradiated with visible light, ultraviolet ray or electron beam with an exposure mask (reticle) of the pattern overlapping the resist, to expose the resist to light, so that a desired pattern is formed.
The exposure mask (reticle) is produced by drawing a pattern on an exposure mask using an electron beam drawing machine based on pattern design data (hereinafter, referred to as pattern design data). A mask original plate before a pattern is drawn is called blank mask and in many cases, inorganic thin film is formed of metal, oxide or nitride on a glass substrate. To create a pattern on the blank mask, resist film is created on the blank mask by, for example, coating and exposed to electron beam.
The pattern design data refers to data for disposing cells which constitutes a gate-level logic circuit within an LSI chip using EDA tool based on gate-level logic circuit design data which achieves a desired operation and further designing wiring for connecting them. When a pattern is formed on the blank mask using the electron beam drawing apparatus, preliminarily, mask drawing pattern design data (hereinafter referred to as mask design data) is created using the pattern design data, electron beam drawing apparatus condition and electron beam drawing simulation result data. Next, a pattern formed on the exposure mask using the electron beam drawing apparatus is inspected about whether or not its pattern forming condition is within an allowable range for mask design by using a mask inspecting device and if it is within the allowable range, the procedure proceeds to exposure process which is a next process. If it is out of the allowable range, the electron beam drawing apparatus is adjusted or the mask design data is corrected.
Because the tilt angle and shape of a slope portion of a pattern formed on the semiconductor wafer by the aforementioned exposure unit change depending on the intensity or diaphragm of electron beam of irradiated visible light, ultraviolet ray or electron beam, it is necessary to inspect completeness of the formed pattern by measurement in order to form high accuracy wiring pattern. The CD-SEM has been widely used for this inspection. A dangerous portion on a semiconductor pattern requiring inspection is observed with the SD-SEM as a measuring point and a variety of data such as wiring width of the pattern, a difference relative to pattern design data are computed from that observed image and then, the formed pattern is inspected based on the measured data. In mass production process, a process change is monitored by monitoring measurement data. As for the measuring point, a portion in which a shape change in the formed pattern might affect the chip performance largely is computed using, for example, device/process simulation and its result is stored as measuring point data. Upon inspection, a photographing recipe is created based on the measuring point data.
To form a desired pattern on the wafer as described above, (1) pattern design, (2) pattern formation using a semiconductor manufacturing apparatus, and (3) pattern completeness inspection using the semiconductor inspecting unit are necessary. Diversified data (for example, logic circuit design data, pattern design data, mask design data, mask photographing recipe, mask photographing result, resist pattern photographing recipe, resist pattern photographing result) need to be used in each process depending on requirement. Data for use in processing at each process include data absolutely necessary for each processing and data, which enables to create a more stable photographing recipe by using it and each data, is selected from possessed data and used. However, conventionally, often matching (matching of coordinate systems, scales and the like) among the respective data has not been secured and the respective data have been controlled separately so that they cannot be referred to by one another. For the reason, it is necessary to enter a module for converting each data to an appropriate format in between the respective data or for an operator to input necessary data manually, which is a cause for reducing the throughput of semiconductor pattern design cycle.